Most integrated circuits currently produced are manufactured on thin disks of silicon and/or other semiconductor material (wafers) using “complementary metal oxide semiconductor” (CMOS) technology. A general discussion of CMOS technology can be found in “Silicon Processing for the VLSI Era, Volume 2—Process Integration” by Wolf et al., Lattice Press, 298-367, (1990). In a CMOS circuit, an electric potential applied to a transistor's gate electrode capacitively couples to its channel and controls the current that flows between its source and drain electrodes. The gate electrode is electrically insulated from the channel by the gate dielectric. The gate dielectric has historically utilized SiO2 formed by thermally oxidizing the silicon above the channel. SiO2 dielectrics have many advantages, including their ability to be removed by etching in either gas, plasma or liquid based processes.
The electrical properties of the transistor depend to a significant degree upon the nature of the gate dielectric. In particular, reducing the thickness of the dielectric increases the capacitive coupling between the gate and channel, allowing higher speed transistor operation at lower operating voltages. But, as the thickness of the dielectric is reduced much below about 20 angstroms, quantum tunneling effects tend to increase, allowing an electric current to flow between the gate and channel. This tunneling current is undesirable as it increases the transistor's power requirements and causes undue heat generation.
Excessive tunneling can be alleviated if the capacitive coupling between the gate and channel is increased by increasing the dielectric constant (k) of a fixed “physical” thickness of gate dielectric, tphys. In one approach, then, a portion or all of a gate dielectric layer can be replaced with an equivalent “electrical thickness” of an insulating material having a dielectric constant that is higher than that of silicon dioxide. The equivalent “electrical thickness,” telect, of a high-k gate dielectric is approximately equal to the gate's physical thickness times the ratio of the dielectric constants of SiO2 and the high-k material, kSiO2 and khigh-k, respectively. That is:telect=tphys*(kSiO2/khigh-k)
For example, assume it is desired to form a gate dielectric layer having the electrical capacitance of a silicon dioxide layer that is 10 angstroms thick. Because of quantum tunneling effects, actually using a silicon dioxide layer that is only ten angstroms thick is problematic. However, recognizing that silicon dioxide has a dielectric constant of 3.8, one generally instead can use 20 angstroms of a material whose dielectric constant is 7.6, or 30 angstrom of a material whose dielectric constant is 11.4, etc.
Developing higher k dielectric materials as well as effective methods of using them to make microelectronic devices has been extremely challenging. One challenge has been the quality of the interface between a semiconductor wafer substrate (especially silicon wafer substrates) and the higher k dielectric material. Whereas silicon dioxide tends to provide an excellent electrical interface with semiconductor materials such as silicon, higher k dielectric materials tend to provide a lesser quality interface. The poor quality of the interface tends to impair the electrical performance of the resultant microelectronic in those instances in which a higher k dielectric material is deposited directly onto the silicon.
It has been found by researchers that another dielectric material such as silicon dioxide or the like can provide a buffer, or bridge, between a semiconductor wafer and a high k dielectric material to improve electrical performance when using higher k dielectric materials. Generally, the buffer material is one that provides an electrical interface of a desired quality between the buffer and the semiconductor substrate, and the buffer in turn provides an electrical interface of a desired quality with the higher k dielectric material.
The buffer layer should not be too thick or else the benefits of using a higher k dielectric material may be unduly reduced. Accordingly, it would be desirable to use a very thin layer (typically on the order of about 20 angstroms or less, preferably about 15 angstroms or less, more preferably about 10 angstroms or less) of another suitable bridging dielectric material such as silicon dioxide as such a buffer. As a representative, concrete example, assume it is desired to use a dielectric layer having electrical capacitance comparable to a 10 angstrom thick silicon dioxide layer. Two angstroms, e.g., of silicon dioxide can be used as a buffer. This leaves 8 angstroms of equivalent silicon dioxide still to be made up. This may be provided by using one or more materials with higher dielectric constant(s) that provide an equivalent electrical thickness with respect to silicon dioxide of 8 angstroms. The resultant dielectric system will then be thick enough generally to avoid undue quantum tunneling problems while still providing some electrical capacitance characteristics as if it were 10 angstroms of silicon dioxide. Additionally, the intervening buffer layer helps to ensure that the electrical couplings between the substrate and the buffer, and then the buffer to the higher k material pass muster.
Of course, even though this example used a buffer layer having a thickness of 2 angstroms, other buffer thicknesses could be used depending upon factors such as the nature of the buffer material(s), the nature of the high k material(s), the desired electrical properties, thickness constraints, and the like. Thus, if the buffer layer were to be 6 angstroms thick, then only additional material that is the equivalent of 4 angstroms of silicon dioxide would need to be used to achieve the 10 angstrom standard used above as an illustration. Other standards, of course, may be used as well. Thus, one might desire to use a dielectric system that has the equivalent performance of 5 angstroms of silicon dioxide, or perhaps 15 angstroms of silicon dioxide, etc.
Unfortunately, it has been very difficult to fabricate extremely thin silicon dioxide layers (e.g., those having a thickness below about 10 angstroms) with desired uniformity characteristics. Lack of uniformity can impair electrical properties of the resultant devices. Thus, maintaining uniformity is very desirable, especially when manufacturing devices with smaller features such as those devices whose gate dielectric layers are comprised of silicon dioxide and/or other dielectric materials and having an equivalent thickness of about 20 angstroms or less, preferably about 15 angstroms or less, and more preferably, about 10 angstroms or less of silicon dioxide.
Thus, there is a strong need and desire in the industry to develop materials and/or methodologies that allow very thin, highly uniform dielectric layers to be formed with high precision.